1. Field of the Invention
The present invention relates to a memory system and memory modules, and more particularly, to a two channel memory system having a shared control and address bus and memory modules used therefor.
2. Description of the Related Art
Memory devices continue to be developed with a higher degree of integration, and with larger capacity based on the increased degree of integration. At the same time, central processing units (CPU) at the centers of computer systems continue to be developed to operate at increased speed. As a result, the disparity between the operation speed of the CPU and the operation speed of the memory continues to increase to a point where, in contemporary systems, the operation speed of the memory device tends to restrict the overall performance of the computer system.
Accordingly, in order to increase the operation speed of the computer system, research has been conducted for the development of high performance memory systems as well as high speed memory devices. Development of high performance memory systems is generally focused on constructing memories capable of inputting and outputting a greater amount of data within a unit time. In order to increase the operation speed of the memory system, a high speed memory device must be first developed. However, interface architectures of memory modules and buses, which can increase system operation speed for connecting the memory device to external components, can also be very important. That is to say, technologies having to do with the arrangement of communication buses and construction of the memory modules used for installing the memory devices on the buses, are very important.
Bandwidth of the memory device, meaning the amount of data input to and output from the memory device within a unit time, is dependent on the width of the data bus and operation speed of the memory device and the data bus. The width of the data bus is affected by the physical area of a system memory region or the spatial arrangement of bus lines. The operation speed of the data bus is affected by the electrical high frequency characteristic of the data bus. Therefore, in order to improve the bandwidth, that is, in order to increase the operation speed of the memory system, ways of making the utmost use of the restricted space assigned to the memory region in the computer system and satisfying various electrical characteristics that are in question in the high frequency regime, must be found.
It is an object of the present invention to provide a memory system capable of increasing the operation speed of a data bus and capable of readily extending the width of the data bus.
It is another object of the present invention to provide a memory module capable of improving the operation speed of a data bus and capable of readily extending the width of the data bus.
Accordingly, to achieve the first object, there is provided a memory system, comprising a system board; a memory controller on the system board; a plurality of memory modules on the system board; a common control and address bus extending from the memory controller; data buses of a first channel extending from the memory controller; and data buses of a second channel extending from the memory controller. The memory modules of a first group are coupled to the data buses of the first channel and the memory modules of a second group are coupled to the data buses of the second channel. The memory modules of the first and second groups share the common control and address bus.
The memory modules can be arranged so that some parts of the memory modules overlap each other. The memory modules of the first group and the memory modules of the second group can also be arranged to cross each other. In a preferred embodiment, the memory modules of the first group and the memory modules of the second group are identical in configuration. Alternatively, the memory modules of the first group and the memory modules of the second group can be configured as mirror images of each other.
Each of the memory modules may comprise a plurality of memory devices mounted on the memory module; a signal input and output portion positioned on a side of the memory module, the signal input and output portion for connecting the memory module to a connector on the system board; a buffer mounted on the memory module; and a control and address bus connected between the signal input and output portion and the buffer. In this embodiment, the memory devices are preferably sequentially connected to the output line of the buffer so that a signal passing through the control and address bus is input to the respective memory devices at time intervals through the buffer. The control and address bus may be input through an input pin of the signal input and output portion, passes through the buffer, and is output through an output pin of the signal input and output portion, which is in the form of a short loop-through configuration. Alternatively, the control and address bus may diverge from the common control and address bus on the system board, which is in the form of a stub configuration.
Each of the memory modules may further comprise a plurality of data buses formed between the input pin and the output pin of the signal input and output portion in the form of the short loop-through configuration and connected to at least one memory device.
The control and address bus and the buffer may be arranged on a side of the memory module, and extend vertically from an edge of the memory module on which the signal input and output portion is positioned.
A register may be mounted on the memory module instead of the buffer.
The data buses of the first channel may be arranged on the left side and the data buses of the second channel may be arranged on the right side of the common control and address bus.
In another aspect, the present invention comprises a memory system, comprising: a system board; a memory controller on the system board; a plurality of memory modules on the system board; a common control and address bus extending from the memory controller; and data buses of a first channel and data buses of a second channel, extending from the memory controller and alternately arranged from side to side in the same direction as the extension of the common control and address bus. Memory modules of the a group are loaded in the data buses of the first channel and memory modules of a second group are loaded in the data buses of the second channel, the memory modules of the first and second groups being coupled to the common control and address bus, and the memory modules of the first group and the memory modules of the second group being alternately arranged in orientation.